1. Field of the Invention
The present invention generally relates to a successive approximation register (SAR) analog-to-digital converter (ADC), and more particularly to an asynchronous SAR ADC.
2. Description of Related Art
A successive approximation register (SAR) analog-to-digital converter (ADC) is one of a variety of ADCs that covert an analog signal to a digital equivalent of the signal. The SAR ADC performs conversion by comparison and searching through all possible quantization levels to obtain a digital output. The SAR ADC requires less silicon area and associated cost than other ADC architectures. However, the SAR ADC needs more cycles to obtain the digital output, and therefore does not fit for high speed applications.
An asynchronous SAR ADC has been disclosed to speed up the operation of the SAR ADC. However, the conventional asynchronous SAR ADC may begin the comparison even some capacitors have not even been stable, thus resulting in incomplete settling that generates erroneous digital output.
For the reason that conventional SAR ADCs could not effectively and correctly speed up the operation, a need has arisen to propose a novel SAR ADC to overcome the disadvantages of the conventional SAR ADCs.